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Ordering number : EN *5753
CMOS LSI
LC8213K
Image Data Compression/Expansion Processor
Preliminary Overview
The LC8213K compresses and expands the binary image data used in fax and similar applications and can be used in office automation equipment such as G3 or G4 facsimile systems, image filing systems, digital copiers, and engineering workstations. The LC8213K supports encoding methods that conform to the MH (Modified Huffman), MR (Modified relative element address designate), and MMR (Modified MR) encoding techniques as stipulated in the ITU-T T.4 and T.6 recommendations.
Package Dimensions
unit: mm 3174-QFP80E
[LC8213K]
Features
* Conforms to the ITU-T T.4 and T.6 MH, MR, and MMR encoding methods. * Supports G3 and G4 facsimile. * Handles up to 64k bits in the main scan direction. * Line skip mode * 8/16-bit image memory bus, 8-bit CPU bus * Supports data transfers between the CPU bus and the image memory bus. * DMA transfer function for data transfers between image memory and I/O devices * Executes encoding processing and DMA transfers simultaneously * System clock frequency: Up to 25 MHz * CMOS structure supporting low power dissipation
SANYO: QIP80E
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input and output voltages Allowable power dissipation Operating temperature Storage temperature Soldering conditions Symbol VDD max VI, VO Pd max Topr Tstg Hand soldering: 3 seconds Reflow soldering: 10 seconds Ta 70C Condition Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 500 -30 to +70 -55 to +125 350 235 Unit V V mW C C C C
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93097HA (OT) No. 5753-1/5
LC8213K Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 4.5 0 typ 5.0 max 5.5 VDD Unit V V
DC Characteristics at Ta = -30 to +70C, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input leakage current Output high-level voltage Output low-level voltage Output leakage current Input clock frequency Current drain Symbol VIH1 VIL1 IL VOH VOL IOZ fCLK IDD IOH = -4 mA IOL = 4 mA For pins in the high-impedance output state CLK 10 -10 -10 2.4 0.4 +10 25 20 Conditions Ratings min 2.2 0.8 +10 typ max Unit V V A V V A MHz mA
Block Diagram
MA23 to MA16 MA/MD15 to MA/MD0 A2 to A0 D7 to D0
TEST4 to TEST0
* CPU interface This circuit is a general-purpose 8-bit CPU interface. The operating mode and other aspects are set by accessing the interface registers and the parameter registers. * Sequence controller Controls the functional blocks in the IC according to the encoding or decoding algorithm being used. * Encoder Generates the codes in the various modes by recognizing inflection points in the image data. Encoded data is passed to the data bus through an 8-bit 4-word encoding FIFO (EFIFO). * Decoder Recognizes the codes in the various modes and recovers the original image data. Image data is passed to the data bus through a decoding FIFO (DFIFO). * Image bus interface Controls reads from and writes to image memory as well as DMA transfers on the image memory bus.
No. 5753-2/5
LC8213K Switching Characteristics at VDD = 2.7 to 5.5 V, Ta = -20 to +75C, VSS = 0 V
I: Input pin O: Output pin B: Bi-directional pin P: Power supply pin NC: No connection Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 BREQ BACK IDREQ IDACK AEN AST MDEN MRD MWR IORD IOWR LDE UDE READY RESET CLK VSS TEST4 VDD TEST3 TEST2 TEST1 TEST0 VDD IREQ DREQ DACK D7 D6 D5 D4 VSS D3 D2 D1 D0 Pin name CS RD WR A2 A1 A0 VDD I/O I I I I I I P NC B B B B P B B B B NC P O O I NC NC NC NC I I P I P I I I I NC O I I O O O O O O O O O O I Bus request signal for the image bus Acknowledge signal for the image bus DMA request signal from I/O devices DMA acknowledge signal to I/O devices Address enable Address strobe Memory data enable Image memory read signal Image memory write signal I/O device read signal I/O device write signal Image bus lower byte valid signal Image bus upper byte valid signal Ready signal Test pin Reset signal input Clock input Ground Test pin Power supply Power supply Interrupt request signal DMA request signal output to external DMA controller DMA acknowledge signal input from external DMA controller Data bus Ground Data bus Power supply Address inputs Chip select signal Read signal from the CPU Write signal from the CPU Function
Continued on next page.
No. 5753-3/5
LC8213K
Continued from preceding page.
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin name DTC VSS VDD MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA/MD15 VSS MA/MD14 MA/MD13 MA/MD12 MA/MD11 MA/MD10 MA/MD9 MA/MD8 MA/MD7 VSS VDD MA/MD6 MA/MD5 MA/MD4 MA/MD3 MA/MD2 MA/MD1 MA/MD0 I/O O P P O O O O O O O O B P B B B B B B B B P P B B B B B B B Lower 16 bits of the image memory address/16-bit data bus Ground Power supply Lower 16 bits of the image memory address/16-bit data bus Lower 16 bits of the image memory address/16-bit data bus Ground Upper 8 bits of the image memory address DMA transfer complete signal Ground Power supply Function
Functional Description * Encoding method Conforms to the MH, MR, and MMR encoding methods of the ITU-T T.4 and T.6 recommendations, which are the standards for G3 and G4 facsimile. * Processing modes Processing is performed in block units, and the number of lines processed can be set to be up to 64k lines. Processing can also be performed in single line units. The LC8213K includes two FIFO systems, one for encoding and one for decoding, so it is also possible to perform encoding and decoding alternately in units of several lines. In encoding mode, data is read out sequentially from the image memory start address loaded into a register and encoded. The encoded data is written to the encoding FIFO. The CPU is interrupted after the specified number of lines of data have been encoded. In decoding mode, encoded data is read out of the decoding FIFO and decoded. The image data is recovered and written to image memory. The CPU is interrupted after the specified number of lines of data have been decoded or a decoding error occurs. * Line skip mode This is a mode in which the amount of code for a completely white line is set to half the set minimum number of transmission bits. A line skip bit, which is used to recognize that a line is completely white, is added after the EOL code, and fill bits are added so that the amount of code is one half the minimum number of transmission bits. For lines that are not all white, the normal coded data is transmitted after the line skip bit.
No. 5753-4/5
LC8213K * CPU interface The LC8213K has an 8-bit data bus. Various aspects of the operating mode can be set by accessing the interface registers. Since the LC8213K provides interface pins for a DMA controller, DMA transfers with memory on the CPU bus are supported. * Image memory interface The image memory has a 16-MB address space. A data bus width of either 8 or 16 bits can be selected. * DMA transfer function This function performs DMA transfers between image memory and I/O devices using the on-chip DMA controller. The number of lines of data transferred can be set to any value up to 64k lines. * Data transfers Data can be transferred between the CPU bus and the image memory bus without encoding or decoding. * Pad bit processing Applications can select whether or not to perform pad bit processing. Pad bit processing consists of adding bits set to 0 at the end of each line of encoded data so that the data for that line is an even multiple of 8 bits. * Parameter settings The LC8213K supports the following parameters, which can be set to any value in the indicated range. * Number of bits processed on a single line (in byte units): 1 to 8k bytes * Source document width (in byte units): * Number of lines processed: * Minimum number of bits transmitted per line: * K parameter for MR encoding: * Number of lines handled in DMA transfers: * Number of EOL codes that form the RTC code: 1 to 8k bytes 1 to 64k lines 0 to 64k bits 0 to 64k 1 to 64k lines 0 to 255
Since the source document width and the number of bits processed on a single line can be set separately, the LC8213K supports encoding or decoding the data for a subsection of the source document.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1997. Specifications and information herein are subject to change without notice. No. 5753-5/5

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